OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] - Rev 25

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 uart transmitter state handling improved jsauermann 3516d 06h /cpu_lecture/trunk/
24 write updated SP in interrupt opcode jsauermann 3540d 04h /cpu_lecture/trunk/
23 fixed bugs in interrupt vector jsauermann 3541d 07h /cpu_lecture/trunk/
22 aligned I/O port numbers to real mega8 jsauermann 3541d 13h /cpu_lecture/trunk/
21 fixed bug in Sign bit computation for SUB and CP instructions jsauermann 3543d 07h /cpu_lecture/trunk/
20 readability of 95xx instructions improved jsauermann 3575d 04h /cpu_lecture/trunk/
19 another bug in the decoding of two-cycle instructions fixed jsauermann 3575d 04h /cpu_lecture/trunk/
18 fixed a bug that caused double execution of some 95xx instructions jsauermann 3578d 06h /cpu_lecture/trunk/
17 fixed missing carry flag for ROR instruction jsauermann 3582d 04h /cpu_lecture/trunk/
16 fixed missing RD_M signal for IN instruction jsauermann 3591d 06h /cpu_lecture/trunk/
15 fixed SP auto inc/dec problem jsauermann 3591d 08h /cpu_lecture/trunk/
14 fixed wrong Q_RSEL for LDD instruction jsauermann 3593d 04h /cpu_lecture/trunk/
13 fixed fault in LDD/STD decoding jsauermann 3594d 04h /cpu_lecture/trunk/
12 fixed bug in decoding of I/O address for SP jsauermann 3595d 04h /cpu_lecture/trunk/
11 fixed fault is BSET/BCLR instruction jsauermann 3597d 04h /cpu_lecture/trunk/
10 wait decoder fault fixed jsauermann 3597d 10h /cpu_lecture/trunk/
9 renamed 'main' to 'hello' in build commands jsauermann 3598d 06h /cpu_lecture/trunk/
8 picture quality slightly improved jsauermann 3598d 10h /cpu_lecture/trunk/
7 support multiple port sizes in make_mem jsauermann 3598d 12h /cpu_lecture/trunk/
6 support multiple port sizes in make_mem jsauermann 3598d 12h /cpu_lecture/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.