OpenCores
URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] - Rev 7

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
7 Fix CL,CWL and AL parameter slai 3900d 11h /ddr3_synthesizable_bfm/
6 Added Mode Register Value dump slai 3900d 11h /ddr3_synthesizable_bfm/
5 Removed some wrongly checked in backup files slai 3900d 17h /ddr3_synthesizable_bfm/
4 Added debug message for MR0 slai 3900d 17h /ddr3_synthesizable_bfm/
3 Added ability to handle up to 8 opened bank & uses DM signals slai 3901d 19h /ddr3_synthesizable_bfm/
2 Initial Check In slai 3901d 19h /ddr3_synthesizable_bfm/
1 The project and the structure was created root 3904d 04h /ddr3_synthesizable_bfm/

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.