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URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] - Rev 10

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Rev Log message Author Age Path
10 v1.01.0030: changed internal counter range to (CNT_VAL+1) to avoid adder flip-over. jdoin 4574d 03h /debouncer_vhdl/
9 Clarified the licensing.
Added SVN directory for the license text.
Changed the LGPL url at the rtl code header.
Included the LGPL 3.0 text "lgpl.txt"
jdoin 4594d 07h /debouncer_vhdl/
8 Updated verification circuit and comments. jdoin 4608d 20h /debouncer_vhdl/
7 - Changed verification project to have all debug signals to fit on a 16 digital signals for the Tek MSO2014 scope.
- Added scope photos of verified circuit
jdoin 4612d 21h /debouncer_vhdl/
6 - fixed some minor comments errors;
- added ISE report files;
- added generated bitgen file (zipped) to test in the Digilent Atlys board;
jdoin 4613d 18h /debouncer_vhdl/
5 cleaned-up XISE files jdoin 4613d 21h /debouncer_vhdl/
4 v1.01.0026 [JD]:
- removed remnants of SPI_MASTER_SLAVE project from ISE project files.
- added pinlock constraint for strobe output for FPGA test.
jdoin 4613d 22h /debouncer_vhdl/
3 v1.01.0025 [JD]:
- added a pipeline delay for new data strobe output.
- included a complete verification project, for simulation and FPGA verification.
jdoin 4613d 22h /debouncer_vhdl/
2 v1.00.0020 [JD]: vhdl file for the debouncer loaded. No simulation testbench yet. The file debouncer_vhdl/trunk/rtl/grp_debouncer.vhd is tested and verified in hardware. jdoin 4614d 08h /debouncer_vhdl/
1 The project and the structure was created root 4614d 17h /debouncer_vhdl/

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