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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 4425d 20h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4488d 17h /
366 Readded eth_top.v with a deprecation warning olof 4612d 21h /
365 Whitespace cleanup olof 4613d 20h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4614d 18h /
363 quartus project files unneback 4615d 02h /
362 added Makefiles to build project unneback 4615d 03h /
361 created branch unneback unneback 4615d 03h /
360 Added partial implementation of the debug register from ORPSoC olof 4616d 01h /
359 Verilator linting fixes olof 4618d 04h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4619d 18h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4619d 18h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4619d 20h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4619d 21h /
354 Whitespace cleanup olof 4619d 21h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4621d 22h /
352 Removed delayed assignments from rtl code olof 4626d 04h /
351 Turn defines into parameters in eth_cop olof 4634d 18h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4634d 19h /
349 Make all parameters configurable from top level olof 4635d 19h /

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