OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 368

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2626d 05h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2689d 02h /
366 Readded eth_top.v with a deprecation warning olof 2813d 06h /
365 Whitespace cleanup olof 2814d 05h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2815d 03h /
363 quartus project files unneback 2815d 11h /
362 added Makefiles to build project unneback 2815d 12h /
361 created branch unneback unneback 2815d 12h /
360 Added partial implementation of the debug register from ORPSoC olof 2816d 10h /
359 Verilator linting fixes olof 2818d 13h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2820d 03h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2820d 03h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2820d 05h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 2820d 05h /
354 Whitespace cleanup olof 2820d 06h /
353 Inherit fixes for bit width of constants from ORPSoC olof 2822d 07h /
352 Removed delayed assignments from rtl code olof 2826d 13h /
351 Turn defines into parameters in eth_cop olof 2835d 03h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 2835d 04h /
349 Make all parameters configurable from top level olof 2836d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.