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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2716d 07h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2779d 04h /
366 Readded eth_top.v with a deprecation warning olof 2903d 08h /
365 Whitespace cleanup olof 2904d 07h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2905d 05h /
363 quartus project files unneback 2905d 13h /
362 added Makefiles to build project unneback 2905d 14h /
361 created branch unneback unneback 2905d 14h /
360 Added partial implementation of the debug register from ORPSoC olof 2906d 12h /
359 Verilator linting fixes olof 2908d 15h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2910d 05h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2910d 05h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2910d 07h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 2910d 08h /
354 Whitespace cleanup olof 2910d 08h /
353 Inherit fixes for bit width of constants from ORPSoC olof 2912d 09h /
352 Removed delayed assignments from rtl code olof 2916d 15h /
351 Turn defines into parameters in eth_cop olof 2925d 05h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 2925d 06h /
349 Make all parameters configurable from top level olof 2926d 06h /

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