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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2681d 10h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2744d 07h /
366 Readded eth_top.v with a deprecation warning olof 2868d 11h /
365 Whitespace cleanup olof 2869d 10h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2870d 08h /
363 quartus project files unneback 2870d 16h /
362 added Makefiles to build project unneback 2870d 17h /
361 created branch unneback unneback 2870d 17h /
360 Added partial implementation of the debug register from ORPSoC olof 2871d 15h /
359 Verilator linting fixes olof 2873d 18h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2875d 08h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2875d 08h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2875d 10h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 2875d 10h /
354 Whitespace cleanup olof 2875d 11h /
353 Inherit fixes for bit width of constants from ORPSoC olof 2877d 12h /
352 Removed delayed assignments from rtl code olof 2881d 18h /
351 Turn defines into parameters in eth_cop olof 2890d 08h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 2890d 09h /
349 Make all parameters configurable from top level olof 2891d 09h /

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