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Rev Log message Author Age Path
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7932d 12h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7933d 02h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7933d 05h /
109 Comment removed. mohor 7933d 05h /
108 Testbench supports unaligned accesses. mohor 8000d 15h /
107 TX_BUF_BASE changed. mohor 8000d 15h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8000d 15h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8009d 17h /
104 FCS should not be included in NibbleMinFl. mohor 8011d 11h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8011d 11h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8011d 11h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8011d 12h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8011d 12h /
99 Document revised. mohor 8018d 10h /
98 Document revised. mohor 8018d 11h /
97 Small typo fixed. lampret 8035d 09h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8039d 09h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8039d 12h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8039d 12h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8044d 10h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8045d 13h /
91 Comments in Slovene language removed. mohor 8045d 13h /
90 casex changed with case, fifo reset changed. mohor 8045d 13h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.
mohor 8049d 11h /
88 rx_fifo was not always cleared ok. Fixed. mohor 8055d 09h /
87 Status was not latched correctly sometimes. Fixed. mohor 8055d 12h /
86 Big Endian problem when sending frames fixed. mohor 8056d 19h /
85 Log info was missing. mohor 8062d 04h /
84 LinkFail signal was not latching appropriate bit. mohor 8062d 04h /
83 MAC address recognition was not correct (bytes swaped). mohor 8062d 04h /

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