OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 126

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
126 InvalidSymbol generation changed. mohor 7916d 16h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7916d 16h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7916d 17h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7918d 18h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7918d 18h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7918d 18h /
120 Unused files removed. mohor 7918d 19h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7918d 19h /
118 ShiftEnded synchronization changed. mohor 7922d 10h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7922d 20h /
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7922d 20h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7923d 18h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7924d 15h /
113 RxPointer bug fixed. mohor 7931d 07h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7931d 21h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7932d 10h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7932d 13h /
109 Comment removed. mohor 7932d 14h /
108 Testbench supports unaligned accesses. mohor 8000d 00h /
107 TX_BUF_BASE changed. mohor 8000d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.