OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 127

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6321d 09h /
126 InvalidSymbol generation changed. mohor 6321d 09h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6321d 09h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6321d 10h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 6323d 10h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6323d 10h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6323d 10h /
120 Unused files removed. mohor 6323d 12h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6323d 12h /
118 ShiftEnded synchronization changed. mohor 6327d 02h /
117 Clock mrx_clk set to 2.5 MHz. mohor 6327d 13h /
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6327d 13h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6328d 11h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6329d 08h /
113 RxPointer bug fixed. mohor 6336d 00h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6336d 14h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 6337d 03h /
110 m_wb_cyc_o signal released after every single transfer. mohor 6337d 06h /
109 Comment removed. mohor 6337d 07h /
108 Testbench supports unaligned accesses. mohor 6404d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.