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128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 6517d 19h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6517d 19h /
126 InvalidSymbol generation changed. mohor 6517d 19h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 6517d 19h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6517d 20h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 6519d 21h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6519d 21h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6519d 21h /
120 Unused files removed. mohor 6519d 22h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6519d 22h /
118 ShiftEnded synchronization changed. mohor 6523d 12h /
117 Clock mrx_clk set to 2.5 MHz. mohor 6523d 23h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 6523d 23h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6524d 21h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6525d 18h /
113 RxPointer bug fixed. mohor 6532d 10h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6533d 00h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 6533d 13h /
110 m_wb_cyc_o signal released after every single transfer. mohor 6533d 16h /
109 Comment removed. mohor 6533d 17h /

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