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Rev Log message Author Age Path
109 Comment removed. mohor 6955d 00h /
108 Testbench supports unaligned accesses. mohor 7022d 10h /
107 TX_BUF_BASE changed. mohor 7022d 10h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7022d 10h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7031d 12h /
104 FCS should not be included in NibbleMinFl. mohor 7033d 06h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7033d 06h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7033d 06h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7033d 07h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7033d 07h /

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