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Rev Log message Author Age Path
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7525d 11h /
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7525d 12h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7545d 11h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7545d 11h /
126 InvalidSymbol generation changed. mohor 7545d 11h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7545d 11h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7545d 12h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7547d 13h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7547d 13h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7547d 13h /
120 Unused files removed. mohor 7547d 14h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7547d 14h /
118 ShiftEnded synchronization changed. mohor 7551d 05h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7551d 15h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 7551d 15h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7552d 13h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7553d 10h /
113 RxPointer bug fixed. mohor 7560d 02h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7560d 16h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7561d 05h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7561d 08h /
109 Comment removed. mohor 7561d 09h /
108 Testbench supports unaligned accesses. mohor 7628d 19h /
107 TX_BUF_BASE changed. mohor 7628d 19h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7628d 19h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7637d 20h /
104 FCS should not be included in NibbleMinFl. mohor 7639d 14h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7639d 15h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7639d 15h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7639d 15h /

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