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Rev Log message Author Age Path
110 m_wb_cyc_o signal released after every single transfer. mohor 7567d 06h /
109 Comment removed. mohor 7567d 07h /
108 Testbench supports unaligned accesses. mohor 7634d 17h /
107 TX_BUF_BASE changed. mohor 7634d 17h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7634d 17h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7643d 18h /
104 FCS should not be included in NibbleMinFl. mohor 7645d 12h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7645d 13h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7645d 13h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7645d 13h /

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