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Rev Log message Author Age Path
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7095d 11h /
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7095d 11h /
131 LinkFail signal was not latching appropriate bit. mohor 7095d 11h /
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7095d 12h /
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7095d 12h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7115d 11h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7115d 11h /
126 InvalidSymbol generation changed. mohor 7115d 11h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7115d 11h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7115d 12h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7117d 13h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7117d 13h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7117d 13h /
120 Unused files removed. mohor 7117d 14h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7117d 14h /
118 ShiftEnded synchronization changed. mohor 7121d 05h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7121d 16h /
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7121d 16h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7122d 14h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7123d 11h /
113 RxPointer bug fixed. mohor 7130d 03h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7130d 17h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7131d 06h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7131d 09h /
109 Comment removed. mohor 7131d 10h /
108 Testbench supports unaligned accesses. mohor 7198d 19h /
107 TX_BUF_BASE changed. mohor 7198d 19h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7198d 19h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7207d 21h /
104 FCS should not be included in NibbleMinFl. mohor 7209d 15h /

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