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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7246d 09h /
126 InvalidSymbol generation changed. mohor 7246d 09h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7246d 09h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7246d 10h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7248d 11h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7248d 11h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7248d 11h /
120 Unused files removed. mohor 7248d 12h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7248d 12h /
118 ShiftEnded synchronization changed. mohor 7252d 03h /

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