URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 152

Rev	Log message	Author	Age	Path
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7919d 00h	/
131	LinkFail signal was not latching appropriate bit.	mohor	7919d 00h	/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	7919d 00h	/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7919d 01h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7939d 00h	/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7939d 00h	/
126	InvalidSymbol generation changed.	mohor	7939d 00h	/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7939d 00h	/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7939d 01h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7941d 02h	/