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Rev Log message Author Age Path
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7298d 22h /
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7298d 22h /
131 LinkFail signal was not latching appropriate bit. mohor 7298d 22h /
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7298d 23h /
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7298d 23h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7318d 22h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7318d 22h /
126 InvalidSymbol generation changed. mohor 7318d 22h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7318d 22h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7318d 23h /

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