URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 180

Rev	Log message	Author	Age	Path
180	Bench outputs data to display every 128 bytes.	mohor	7887d 07h	/
179	Beautiful tests merget together	mohor	7887d 08h	/
178	Rearanged testcases	mohor	7887d 08h	/
177	Bug in MIIM fixed.	mohor	7887d 12h	/
176	lists changed to new directory structure	mohor	7887d 13h	/
175	Script fixed to new dir structure	mohor	7887d 14h	/
174	Directory keeper	mohor	7887d 14h	/
173	Keeps the directory	mohor	7887d 14h	/
172	NCSIM simulation environment added to cvs	mohor	7887d 14h	/
171	NCSIM simulation environment added.	mohor	7887d 14h	/
170	Headers changed.	mohor	7887d 14h	/
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	7887d 15h	/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7888d 12h	/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7889d 12h	/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7890d 13h	/
165	HASH improvement needed.	mohor	7890d 16h	/
164	Ethernet debug registers removed.	mohor	7890d 16h	/
163	Another temporary version. Core is almost finished. Testbench not included, yet"	mohor	7891d 08h	/
162	Another temporary version. Core is almost finished. Testbench not included, yet.	mohor	7891d 08h	/
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7891d 14h	/