OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 206

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
206 Virtual Silicon RAM added to the simulation. mohor 7856d 14h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7856d 15h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7856d 15h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7856d 15h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7859d 16h /
201 Core size added to the document. mohor 7859d 17h /
200 File with lower case checked in instead. mohor 7859d 17h /
199 Datasheet name changed to lower case name. mohor 7859d 17h /
198 Removed file. File with name in lower case will be added instead. mohor 7859d 17h /
197 Ethernet Data Sheet. mohor 7859d 17h /
196 Ethernet product brief. mohor 7859d 18h /
195 Product brief removed because it is the same as Datasheet. mohor 7859d 18h /
194 Full duplex tests modified and testbench bug repaired. tadej 7859d 19h /
193 Temp version (backup). mohor 7859d 21h /
192 Some additional reports added tadej 7861d 16h /
191 Bug repaired in eth_phy device tadej 7861d 16h /
190 Several information added to the file. mohor 7861d 17h /
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7861d 17h /
188 PHY changed. tadej 7862d 13h /
187 _info file added. mohor 7862d 14h /
186 Macro for testbench (DO file). mohor 7862d 14h /
185 Directory keeper. mohor 7862d 15h /
184 Modelsim simulation environment should be ready now. mohor 7862d 15h /
183 Modelsim environment added. mohor 7862d 15h /
182 Full duplex test improved. tadej 7863d 16h /
181 MIIM test look better. mohor 7863d 18h /
180 Bench outputs data to display every 128 bytes. mohor 7866d 14h /
179 Beautiful tests merget together mohor 7866d 15h /
178 Rearanged testcases mohor 7866d 15h /
177 Bug in MIIM fixed. mohor 7866d 19h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.