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Rev Log message Author Age Path
215 Bist supported. mohor 7421d 06h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7422d 02h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7422d 02h /
212 Minor $display change. mohor 7422d 02h /
211 Bist added. mohor 7422d 02h /
210 BIST added. mohor 7422d 02h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7423d 05h /
208 Virtual Silicon RAMs moved to lib directory tadej 7438d 23h /
207 Virtual Silicon RAM support fixed tadej 7438d 23h /
206 Virtual Silicon RAM added to the simulation. mohor 7438d 23h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7439d 00h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7439d 00h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7439d 00h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7442d 01h /
201 Core size added to the document. mohor 7442d 02h /
200 File with lower case checked in instead. mohor 7442d 02h /
199 Datasheet name changed to lower case name. mohor 7442d 02h /
198 Removed file. File with name in lower case will be added instead. mohor 7442d 02h /
197 Ethernet Data Sheet. mohor 7442d 02h /
196 Ethernet product brief. mohor 7442d 03h /

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