Subversion Repositories ethmac

[/] - Rev 217


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
217 Bist supported. mohor 7730d 16h /
216 Bist signals added. mohor 7730d 16h /
215 Bist supported. mohor 7730d 17h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7731d 13h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7731d 13h /
212 Minor $display change. mohor 7731d 13h /
211 Bist added. mohor 7731d 13h /
210 BIST added. mohor 7731d 13h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7732d 16h /
208 Virtual Silicon RAMs moved to lib directory tadej 7748d 10h /
207 Virtual Silicon RAM support fixed tadej 7748d 10h /
206 Virtual Silicon RAM added to the simulation. mohor 7748d 11h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7748d 11h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7748d 11h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7748d 11h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7751d 13h /
201 Core size added to the document. mohor 7751d 13h /
200 File with lower case checked in instead. mohor 7751d 13h /
199 Datasheet name changed to lower case name. mohor 7751d 13h /
198 Removed file. File with name in lower case will be added instead. mohor 7751d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.