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Rev Log message Author Age Path
218 Typo error fixed. (When using Bist) mohor 6474d 20h /
217 Bist supported. mohor 6474d 20h /
216 Bist signals added. mohor 6474d 20h /
215 Bist supported. mohor 6474d 21h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6475d 17h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6475d 17h /
212 Minor $display change. mohor 6475d 17h /
211 Bist added. mohor 6475d 17h /
210 BIST added. mohor 6475d 17h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6476d 20h /
208 Virtual Silicon RAMs moved to lib directory tadej 6492d 14h /
207 Virtual Silicon RAM support fixed tadej 6492d 14h /
206 Virtual Silicon RAM added to the simulation. mohor 6492d 14h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6492d 15h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6492d 15h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 6492d 15h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6495d 16h /
201 Core size added to the document. mohor 6495d 17h /
200 File with lower case checked in instead. mohor 6495d 17h /
199 Datasheet name changed to lower case name. mohor 6495d 17h /

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