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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6238d 20h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6241d 20h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6241d 20h /
218 Typo error fixed. (When using Bist) mohor 6241d 22h /
217 Bist supported. mohor 6241d 22h /
216 Bist signals added. mohor 6241d 22h /
215 Bist supported. mohor 6241d 23h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6242d 19h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6242d 19h /
212 Minor $display change. mohor 6242d 19h /
211 Bist added. mohor 6242d 19h /
210 BIST added. mohor 6242d 19h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6243d 23h /
208 Virtual Silicon RAMs moved to lib directory tadej 6259d 16h /
207 Virtual Silicon RAM support fixed tadej 6259d 17h /
206 Virtual Silicon RAM added to the simulation. mohor 6259d 17h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6259d 17h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6259d 17h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6259d 17h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6262d 19h /

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