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Rev Log message Author Age Path
225 Some minor changes. tadejm 7463d 02h /
224 Signals for a wave window in Modelsim. tadejm 7463d 03h /
223 Some code changed due to bug fixes. tadejm 7463d 03h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7467d 01h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7467d 01h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7470d 01h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7470d 01h /
218 Typo error fixed. (When using Bist) mohor 7470d 03h /
217 Bist supported. mohor 7470d 04h /
216 Bist signals added. mohor 7470d 04h /
215 Bist supported. mohor 7470d 04h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7471d 00h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7471d 00h /
212 Minor $display change. mohor 7471d 00h /
211 Bist added. mohor 7471d 01h /
210 BIST added. mohor 7471d 01h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7472d 04h /
208 Virtual Silicon RAMs moved to lib directory tadej 7487d 22h /
207 Virtual Silicon RAM support fixed tadej 7487d 22h /
206 Virtual Silicon RAM added to the simulation. mohor 7487d 22h /

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