OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 232

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
232 fpga define added. mohor 6202d 13h /
231 Description of Core Modules added (figure). mohor 6204d 14h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6208d 11h /
229 case changed to casex. mohor 6208d 11h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6208d 15h /
227 Changed BIST scan signals. tadejm 6208d 15h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6208d 16h /
225 Some minor changes. tadejm 6208d 16h /
224 Signals for a wave window in Modelsim. tadejm 6208d 18h /
223 Some code changed due to bug fixes. tadejm 6208d 18h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6212d 16h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6212d 16h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6215d 16h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6215d 16h /
218 Typo error fixed. (When using Bist) mohor 6215d 18h /
217 Bist supported. mohor 6215d 18h /
216 Bist signals added. mohor 6215d 18h /
215 Bist supported. mohor 6215d 19h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6216d 15h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6216d 15h /
212 Minor $display change. mohor 6216d 15h /
211 Bist added. mohor 6216d 15h /
210 BIST added. mohor 6216d 15h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6217d 19h /
208 Virtual Silicon RAMs moved to lib directory tadej 6233d 13h /
207 Virtual Silicon RAM support fixed tadej 6233d 13h /
206 Virtual Silicon RAM added to the simulation. mohor 6233d 13h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6233d 13h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6233d 14h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6233d 14h /

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.