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Rev Log message Author Age Path
235 rev 4. mohor 6468d 04h /
234 Figure list assed to the revision 3. mohor 6468d 12h /
233 Revision 0.3 released. Some figures added. mohor 6468d 13h /
232 fpga define added. mohor 6473d 08h /
231 Description of Core Modules added (figure). mohor 6475d 09h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6479d 06h /
229 case changed to casex. mohor 6479d 06h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6479d 09h /
227 Changed BIST scan signals. tadejm 6479d 09h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6479d 11h /
225 Some minor changes. tadejm 6479d 11h /
224 Signals for a wave window in Modelsim. tadejm 6479d 12h /
223 Some code changed due to bug fixes. tadejm 6479d 13h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6483d 10h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6483d 10h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6486d 11h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6486d 11h /
218 Typo error fixed. (When using Bist) mohor 6486d 13h /
217 Bist supported. mohor 6486d 13h /
216 Bist signals added. mohor 6486d 13h /

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