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Rev	Log message	Author	Age	Path
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7827d 00h	/
248	wb_rst_i is used for MIIM reset.	mohor	7827d 00h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7830d 03h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7830d 03h	/
245	Rev 1.7.	mohor	7830d 21h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7830d 23h	/
243	Late collision is not reported any more.	tadejm	7831d 05h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7831d 19h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7831d 19h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7831d 19h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7831d 20h	/
238	Defines fixed to use generic RAM by default.	mohor	7844d 00h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7846d 05h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7846d 05h	/
235	rev 4.	mohor	7846d 20h	/
234	Figure list assed to the revision 3.	mohor	7847d 04h	/
233	Revision 0.3 released. Some figures added.	mohor	7847d 04h	/
232	fpga define added.	mohor	7851d 23h	/
231	Description of Core Modules added (figure).	mohor	7854d 00h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7857d 21h	/

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