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Rev Log message Author Age Path
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6545d 09h /
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 6546d 09h /
248 wb_rst_i is used for MIIM reset. mohor 6546d 09h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6549d 12h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6549d 12h /
245 Rev 1.7. mohor 6550d 06h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6550d 08h /
243 Late collision is not reported any more. tadejm 6550d 13h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6551d 04h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6551d 04h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6551d 04h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6551d 04h /
238 Defines fixed to use generic RAM by default. mohor 6563d 08h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6565d 13h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6565d 13h /
235 rev 4. mohor 6566d 04h /
234 Figure list assed to the revision 3. mohor 6566d 12h /
233 Revision 0.3 released. Some figures added. mohor 6566d 13h /
232 fpga define added. mohor 6571d 07h /
231 Description of Core Modules added (figure). mohor 6573d 09h /

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