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Rev	Log message	Author	Age	Path
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7827d 23h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7828d 23h	/
248	wb_rst_i is used for MIIM reset.	mohor	7828d 23h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7832d 02h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7832d 02h	/
245	Rev 1.7.	mohor	7832d 20h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7832d 22h	/
243	Late collision is not reported any more.	tadejm	7833d 04h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7833d 18h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7833d 18h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7833d 19h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7833d 19h	/
238	Defines fixed to use generic RAM by default.	mohor	7845d 23h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7848d 04h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7848d 04h	/
235	rev 4.	mohor	7848d 19h	/
234	Figure list assed to the revision 3.	mohor	7849d 03h	/
233	Revision 0.3 released. Some figures added.	mohor	7849d 03h	/
232	fpga define added.	mohor	7853d 22h	/
231	Description of Core Modules added (figure).	mohor	7855d 23h	/

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[/] - Rev 250

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