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Rev	Log message	Author	Age	Path
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	8100d 03h	/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	8100d 03h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		8101d 03h	/
248	wb_rst_i is used for MIIM reset.	mohor	8101d 03h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		8104d 06h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8104d 06h	/
245	Rev 1.7.	mohor	8105d 00h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8105d 02h	/
243	Late collision is not reported any more.	tadejm	8105d 08h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8105d 22h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	8105d 22h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	8105d 22h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	8105d 22h	/
238	Defines fixed to use generic RAM by default.	mohor	8118d 03h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		8120d 08h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	8120d 08h	/
235	rev 4.	mohor	8120d 23h	/
234	Figure list assed to the revision 3.	mohor	8121d 07h	/
233	Revision 0.3 released. Some figures added.	mohor	8121d 07h	/
232	fpga define added.	mohor	8126d 02h	/

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[/] - Rev 251

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