Subversion Repositories ethmac

[/] - Rev 252


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
252 Just some updates. tadejm 6951d 00h /
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6951d 00h /
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6951d 00h /
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 6952d 00h /
248 wb_rst_i is used for MIIM reset. mohor 6952d 00h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6955d 03h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6955d 03h /
245 Rev 1.7. mohor 6955d 21h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6955d 23h /
243 Late collision is not reported any more. tadejm 6956d 05h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6956d 19h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6956d 19h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6956d 19h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6956d 20h /
238 Defines fixed to use generic RAM by default. mohor 6969d 00h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6971d 05h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6971d 05h /
235 rev 4. mohor 6971d 20h /
234 Figure list assed to the revision 3. mohor 6972d 04h /
233 Revision 0.3 released. Some figures added. mohor 6972d 04h /
232 fpga define added. mohor 6976d 23h /
231 Description of Core Modules added (figure). mohor 6979d 00h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6982d 21h /
229 case changed to casex. mohor 6982d 21h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6983d 01h /
227 Changed BIST scan signals. tadejm 6983d 01h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6983d 02h /
225 Some minor changes. tadejm 6983d 02h /
224 Signals for a wave window in Modelsim. tadejm 6983d 04h /
223 Some code changed due to bug fixes. tadejm 6983d 04h /

powered by: WebSVN 2.1.0

© copyright 1999-2021, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.