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Rev Log message Author Age Path
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 8131d 20h /
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 8132d 20h /
268 Release 1.19. Control frame description changed. mohor 8186d 13h /
267 Full duplex control frames tested. mohor 8186d 16h /
266 Flow control test almost finished. mohor 8191d 14h /
265 This commit was manufactured by cvs2svn to create tag 'rel_13'. 8191d 18h /
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 8191d 18h /
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 8192d 06h /
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 8192d 06h /
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 8192d 06h /
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 8192d 18h /
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 8193d 07h /
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 8193d 08h /
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 8193d 08h /
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 8193d 08h /
255 TPauseRq synchronized to tx_clk. mohor 8193d 08h /
254 Temp version. mohor 8194d 11h /
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 8194d 14h /
252 Just some updates. tadejm 8194d 14h /
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 8194d 14h /

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