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Rev Log message Author Age Path
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 5887d 20h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 5888d 18h /
306 Lapsus fixed (!we -> ~we). simons 5888d 18h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 5910d 15h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5910d 15h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 5937d 01h /
302 mbist signals updated according to newest convention markom 5937d 01h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5947d 17h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 5994d 21h /
299 Artisan RAMs added. mohor 5994d 21h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 6000d 16h /
297 Artisan ram instance added. simons 6000d 16h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 6001d 19h /
295 Few minor changes. tadejm 6001d 19h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6003d 20h /
293 initial. tadejm 6027d 17h /
292 Corrected mistake. tadejm 6027d 17h /
291 initial tadejm 6027d 18h /
290 Additional checking for FAILED tests added - for ATS. tadejm 6027d 19h /
289 This commit was manufactured by cvs2svn to create tag 'rel_18'. 6036d 18h /

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