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Rev Log message Author Age Path
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7420d 01h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7420d 22h /
306 Lapsus fixed (!we -> ~we). simons 7420d 22h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7442d 19h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7442d 19h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7469d 05h /
302 mbist signals updated according to newest convention markom 7469d 05h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7479d 22h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7527d 01h /
299 Artisan RAMs added. mohor 7527d 01h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7532d 21h /
297 Artisan ram instance added. simons 7532d 21h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7534d 00h /
295 Few minor changes. tadejm 7534d 00h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7536d 00h /
293 initial. tadejm 7559d 21h /
292 Corrected mistake. tadejm 7559d 21h /
291 initial tadejm 7559d 22h /
290 Additional checking for FAILED tests added - for ATS. tadejm 7559d 23h /
289 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7568d 22h /

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