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Rev Log message Author Age Path
309 Update file list files for different RAM models with byte select accessing. tadejm 7617d 05h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7617d 05h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7618d 03h /
306 Lapsus fixed (!we -> ~we). simons 7618d 03h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7640d 00h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7640d 00h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7666d 10h /
302 mbist signals updated according to newest convention markom 7666d 10h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7677d 02h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7724d 06h /
299 Artisan RAMs added. mohor 7724d 06h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7730d 01h /
297 Artisan ram instance added. simons 7730d 01h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7731d 04h /
295 Few minor changes. tadejm 7731d 04h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7733d 05h /
293 initial. tadejm 7757d 02h /
292 Corrected mistake. tadejm 7757d 02h /
291 initial tadejm 7757d 03h /
290 Additional checking for FAILED tests added - for ATS. tadejm 7757d 04h /

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