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Rev Log message Author Age Path
311 Update script for running different file list files for different RAM models. tadejm 5893d 06h /
310 More signals. tadejm 5893d 06h /
309 Update file list files for different RAM models with byte select accessing. tadejm 5893d 06h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 5893d 06h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 5894d 04h /
306 Lapsus fixed (!we -> ~we). simons 5894d 04h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 5916d 00h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5916d 00h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 5942d 11h /
302 mbist signals updated according to newest convention markom 5942d 11h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5953d 03h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 6000d 07h /
299 Artisan RAMs added. mohor 6000d 07h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 6006d 02h /
297 Artisan ram instance added. simons 6006d 02h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 6007d 05h /
295 Few minor changes. tadejm 6007d 05h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6009d 06h /
293 initial. tadejm 6033d 03h /
292 Corrected mistake. tadejm 6033d 03h /

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