OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 339

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
339 Added basic support for Icarus Verilog olof 4669d 20h /
338 root 5462d 02h /
337 root 5518d 04h /
336 Added old uploaded documents to new repository. root 5519d 07h /
335 New directory structure. root 5519d 07h /
334 Minor fixes for Icarus simulator. igorm 6967d 09h /
333 Some small fixes + some troubles fixed. igorm 6967d 21h /
332 Case statement improved for synthesys. igorm 6981d 03h /
331 Tests for delayed CRC and defer indication added. igorm 6996d 04h /
330 Warning fixes. igorm 6996d 05h /
329 Defer indication fixed. igorm 6996d 06h /
328 Delayed CRC fixed. igorm 6996d 06h /
327 Defer indication fixed. igorm 6996d 06h /
326 Delayed CRC fixed. igorm 6996d 06h /
325 Defer indication fixed. igorm 6996d 07h /
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 7293d 07h /
323 Accidently deleted line put back. igorm 7293d 07h /
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7297d 02h /
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7297d 02h /
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7297d 06h /
319 Latest Ethernet IP core testbench. tadejm 7328d 01h /
318 Latest Ethernet IP core testbench. tadejm 7328d 01h /
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7337d 08h /
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 7440d 05h /
315 Updated testbench. Some more testcases, some repaired. tadejm 7440d 05h /
314 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7440d 05h /
313 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7440d 05h /
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7440d 05h /
311 Update script for running different file list files for different RAM models. tadejm 7440d 05h /
310 More signals. tadejm 7440d 05h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.