OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 340

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
340 Don't fail if log dir already exists olof 4462d 13h /
339 Added basic support for Icarus Verilog olof 4463d 13h /
338 root 5255d 18h /
337 root 5311d 20h /
336 Added old uploaded documents to new repository. root 5313d 00h /
335 New directory structure. root 5313d 00h /
334 Minor fixes for Icarus simulator. igorm 6761d 02h /
333 Some small fixes + some troubles fixed. igorm 6761d 14h /
332 Case statement improved for synthesys. igorm 6774d 19h /
331 Tests for delayed CRC and defer indication added. igorm 6789d 21h /
330 Warning fixes. igorm 6789d 21h /
329 Defer indication fixed. igorm 6789d 22h /
328 Delayed CRC fixed. igorm 6789d 22h /
327 Defer indication fixed. igorm 6789d 22h /
326 Delayed CRC fixed. igorm 6789d 23h /
325 Defer indication fixed. igorm 6789d 23h /
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 7086d 23h /
323 Accidently deleted line put back. igorm 7086d 23h /
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7090d 18h /
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7090d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.