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Rev Log message Author Age Path
345 Temporarily disable failing tests olof 4658d 12h /
344 bit 9 in phy control register is self clearing olof 4664d 14h /
343 Address miss should not be asserted on short frames olof 4668d 10h /
342 Added cast to avoid inequality when comparing different data types olof 4668d 10h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4668d 11h /
340 Don't fail if log dir already exists olof 4669d 08h /
339 Added basic support for Icarus Verilog olof 4670d 07h /
338 root 5462d 13h /
337 root 5518d 15h /
336 Added old uploaded documents to new repository. root 5519d 18h /
335 New directory structure. root 5519d 18h /
334 Minor fixes for Icarus simulator. igorm 6967d 21h /
333 Some small fixes + some troubles fixed. igorm 6968d 08h /
332 Case statement improved for synthesys. igorm 6981d 14h /
331 Tests for delayed CRC and defer indication added. igorm 6996d 15h /
330 Warning fixes. igorm 6996d 16h /
329 Defer indication fixed. igorm 6996d 17h /
328 Delayed CRC fixed. igorm 6996d 17h /
327 Defer indication fixed. igorm 6996d 17h /
326 Delayed CRC fixed. igorm 6996d 17h /

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