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Rev Log message Author Age Path
348 Added option to dump VCD files olof 4461d 03h /
347 Added information about running with Icarus Verilog olof 4461d 03h /
346 Updated project location olof 4461d 05h /
345 Temporarily disable failing tests olof 4461d 07h /
344 bit 9 in phy control register is self clearing olof 4467d 09h /
343 Address miss should not be asserted on short frames olof 4471d 05h /
342 Added cast to avoid inequality when comparing different data types olof 4471d 05h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4471d 05h /
340 Don't fail if log dir already exists olof 4472d 03h /
339 Added basic support for Icarus Verilog olof 4473d 02h /
338 root 5265d 08h /
337 root 5321d 10h /
336 Added old uploaded documents to new repository. root 5322d 13h /
335 New directory structure. root 5322d 13h /
334 Minor fixes for Icarus simulator. igorm 6770d 15h /
333 Some small fixes + some troubles fixed. igorm 6771d 03h /
332 Case statement improved for synthesys. igorm 6784d 08h /
331 Tests for delayed CRC and defer indication added. igorm 6799d 10h /
330 Warning fixes. igorm 6799d 10h /
329 Defer indication fixed. igorm 6799d 11h /

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