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Rev Log message Author Age Path
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3957d 19h /
349 Make all parameters configurable from top level olof 3958d 20h /
348 Added option to dump VCD files olof 3959d 19h /
347 Added information about running with Icarus Verilog olof 3959d 20h /
346 Updated project location olof 3959d 22h /
345 Temporarily disable failing tests olof 3959d 23h /
344 bit 9 in phy control register is self clearing olof 3966d 01h /
343 Address miss should not be asserted on short frames olof 3969d 21h /
342 Added cast to avoid inequality when comparing different data types olof 3969d 21h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3969d 22h /
340 Don't fail if log dir already exists olof 3970d 19h /
339 Added basic support for Icarus Verilog olof 3971d 18h /
338 root 4764d 00h /
337 root 4820d 02h /
336 Added old uploaded documents to new repository. root 4821d 05h /
335 New directory structure. root 4821d 05h /
334 Minor fixes for Icarus simulator. igorm 6269d 07h /
333 Some small fixes + some troubles fixed. igorm 6269d 19h /
332 Case statement improved for synthesys. igorm 6283d 01h /
331 Tests for delayed CRC and defer indication added. igorm 6298d 02h /

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