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Rev Log message Author Age Path
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4635d 01h /
349 Make all parameters configurable from top level olof 4636d 01h /
348 Added option to dump VCD files olof 4637d 00h /
347 Added information about running with Icarus Verilog olof 4637d 01h /
346 Updated project location olof 4637d 03h /
345 Temporarily disable failing tests olof 4637d 04h /
344 bit 9 in phy control register is self clearing olof 4643d 06h /
343 Address miss should not be asserted on short frames olof 4647d 02h /
342 Added cast to avoid inequality when comparing different data types olof 4647d 03h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4647d 03h /
340 Don't fail if log dir already exists olof 4648d 00h /
339 Added basic support for Icarus Verilog olof 4649d 00h /
338 root 5441d 05h /
337 root 5497d 07h /
336 Added old uploaded documents to new repository. root 5498d 10h /
335 New directory structure. root 5498d 10h /
334 Minor fixes for Icarus simulator. igorm 6946d 13h /
333 Some small fixes + some troubles fixed. igorm 6947d 00h /
332 Case statement improved for synthesys. igorm 6960d 06h /
331 Tests for delayed CRC and defer indication added. igorm 6975d 07h /

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