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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 3109d 12h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3109d 13h /
349 Make all parameters configurable from top level olof 3110d 14h /
348 Added option to dump VCD files olof 3111d 13h /
347 Added information about running with Icarus Verilog olof 3111d 13h /
346 Updated project location olof 3111d 15h /
345 Temporarily disable failing tests olof 3111d 17h /
344 bit 9 in phy control register is self clearing olof 3117d 19h /
343 Address miss should not be asserted on short frames olof 3121d 15h /
342 Added cast to avoid inequality when comparing different data types olof 3121d 15h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3121d 15h /
340 Don't fail if log dir already exists olof 3122d 13h /
339 Added basic support for Icarus Verilog olof 3123d 12h /
338 root 3915d 18h /
337 root 3971d 20h /
336 Added old uploaded documents to new repository. root 3972d 23h /
335 New directory structure. root 3972d 23h /
334 Minor fixes for Icarus simulator. igorm 5421d 01h /
333 Some small fixes + some troubles fixed. igorm 5421d 13h /
332 Case statement improved for synthesys. igorm 5434d 18h /

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