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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 3356d 05h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3356d 06h /
349 Make all parameters configurable from top level olof 3357d 06h /
348 Added option to dump VCD files olof 3358d 05h /
347 Added information about running with Icarus Verilog olof 3358d 06h /
346 Updated project location olof 3358d 08h /
345 Temporarily disable failing tests olof 3358d 09h /
344 bit 9 in phy control register is self clearing olof 3364d 12h /
343 Address miss should not be asserted on short frames olof 3368d 07h /
342 Added cast to avoid inequality when comparing different data types olof 3368d 08h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3368d 08h /
340 Don't fail if log dir already exists olof 3369d 05h /
339 Added basic support for Icarus Verilog olof 3370d 05h /
338 root 4162d 10h /
337 root 4218d 12h /
336 Added old uploaded documents to new repository. root 4219d 16h /
335 New directory structure. root 4219d 16h /
334 Minor fixes for Icarus simulator. igorm 5667d 18h /
333 Some small fixes + some troubles fixed. igorm 5668d 05h /
332 Case statement improved for synthesys. igorm 5681d 11h /

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