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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 4648d 13h /
351 Turn defines into parameters in eth_cop olof 4657d 03h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4657d 04h /
349 Make all parameters configurable from top level olof 4658d 05h /
348 Added option to dump VCD files olof 4659d 04h /
347 Added information about running with Icarus Verilog olof 4659d 04h /
346 Updated project location olof 4659d 06h /
345 Temporarily disable failing tests olof 4659d 08h /
344 bit 9 in phy control register is self clearing olof 4665d 10h /
343 Address miss should not be asserted on short frames olof 4669d 06h /
342 Added cast to avoid inequality when comparing different data types olof 4669d 06h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4669d 06h /
340 Don't fail if log dir already exists olof 4670d 04h /
339 Added basic support for Icarus Verilog olof 4671d 03h /
338 root 5463d 09h /
337 root 5519d 11h /
336 Added old uploaded documents to new repository. root 5520d 14h /
335 New directory structure. root 5520d 14h /
334 Minor fixes for Icarus simulator. igorm 6968d 16h /
333 Some small fixes + some troubles fixed. igorm 6969d 04h /

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