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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3832d 18h /
351 Turn defines into parameters in eth_cop olof 3841d 08h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3841d 09h /
349 Make all parameters configurable from top level olof 3842d 09h /
348 Added option to dump VCD files olof 3843d 08h /
347 Added information about running with Icarus Verilog olof 3843d 09h /
346 Updated project location olof 3843d 11h /
345 Temporarily disable failing tests olof 3843d 12h /
344 bit 9 in phy control register is self clearing olof 3849d 15h /
343 Address miss should not be asserted on short frames olof 3853d 11h /
342 Added cast to avoid inequality when comparing different data types olof 3853d 11h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3853d 11h /
340 Don't fail if log dir already exists olof 3854d 08h /
339 Added basic support for Icarus Verilog olof 3855d 08h /
338 root 4647d 13h /
337 root 4703d 15h /
336 Added old uploaded documents to new repository. root 4704d 19h /
335 New directory structure. root 4704d 19h /
334 Minor fixes for Icarus simulator. igorm 6152d 21h /
333 Some small fixes + some troubles fixed. igorm 6153d 08h /

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