OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 357

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4619d 13h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4619d 15h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4619d 16h /
354 Whitespace cleanup olof 4619d 16h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4621d 18h /
352 Removed delayed assignments from rtl code olof 4626d 00h /
351 Turn defines into parameters in eth_cop olof 4634d 14h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4634d 14h /
349 Make all parameters configurable from top level olof 4635d 15h /
348 Added option to dump VCD files olof 4636d 14h /
347 Added information about running with Icarus Verilog olof 4636d 14h /
346 Updated project location olof 4636d 17h /
345 Temporarily disable failing tests olof 4636d 18h /
344 bit 9 in phy control register is self clearing olof 4642d 20h /
343 Address miss should not be asserted on short frames olof 4646d 16h /
342 Added cast to avoid inequality when comparing different data types olof 4646d 16h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4646d 16h /
340 Don't fail if log dir already exists olof 4647d 14h /
339 Added basic support for Icarus Verilog olof 4648d 13h /
338 root 5440d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.