OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 358

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4911d 06h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4911d 06h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4911d 08h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4911d 09h /
354 Whitespace cleanup olof 4911d 09h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4913d 10h /
352 Removed delayed assignments from rtl code olof 4917d 16h /
351 Turn defines into parameters in eth_cop olof 4926d 06h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4926d 07h /
349 Make all parameters configurable from top level olof 4927d 07h /
348 Added option to dump VCD files olof 4928d 06h /
347 Added information about running with Icarus Verilog olof 4928d 07h /
346 Updated project location olof 4928d 09h /
345 Temporarily disable failing tests olof 4928d 11h /
344 bit 9 in phy control register is self clearing olof 4934d 13h /
343 Address miss should not be asserted on short frames olof 4938d 09h /
342 Added cast to avoid inequality when comparing different data types olof 4938d 09h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4938d 09h /
340 Don't fail if log dir already exists olof 4939d 06h /
339 Added basic support for Icarus Verilog olof 4940d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.