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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4251d 19h /
359 Verilator linting fixes olof 4253d 21h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4255d 11h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4255d 11h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4255d 13h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4255d 14h /
354 Whitespace cleanup olof 4255d 14h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4257d 15h /
352 Removed delayed assignments from rtl code olof 4261d 21h /
351 Turn defines into parameters in eth_cop olof 4270d 11h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4270d 12h /
349 Make all parameters configurable from top level olof 4271d 12h /
348 Added option to dump VCD files olof 4272d 11h /
347 Added information about running with Icarus Verilog olof 4272d 12h /
346 Updated project location olof 4272d 14h /
345 Temporarily disable failing tests olof 4272d 16h /
344 bit 9 in phy control register is self clearing olof 4278d 18h /
343 Address miss should not be asserted on short frames olof 4282d 14h /
342 Added cast to avoid inequality when comparing different data types olof 4282d 14h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4282d 14h /

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