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Rev Log message Author Age Path
362 added Makefiles to build project unneback 5028d 00h /
361 created branch unneback unneback 5028d 00h /
360 Added partial implementation of the debug register from ORPSoC olof 5028d 23h /
359 Verilator linting fixes olof 5031d 01h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 5032d 15h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 5032d 15h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 5032d 17h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 5032d 18h /
354 Whitespace cleanup olof 5032d 18h /
353 Inherit fixes for bit width of constants from ORPSoC olof 5034d 19h /
352 Removed delayed assignments from rtl code olof 5039d 01h /
351 Turn defines into parameters in eth_cop olof 5047d 15h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 5047d 16h /
349 Make all parameters configurable from top level olof 5048d 16h /
348 Added option to dump VCD files olof 5049d 15h /
347 Added information about running with Icarus Verilog olof 5049d 16h /
346 Updated project location olof 5049d 18h /
345 Temporarily disable failing tests olof 5049d 20h /
344 bit 9 in phy control register is self clearing olof 5055d 22h /
343 Address miss should not be asserted on short frames olof 5059d 18h /
342 Added cast to avoid inequality when comparing different data types olof 5059d 18h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 5059d 18h /
340 Don't fail if log dir already exists olof 5060d 15h /
339 Added basic support for Icarus Verilog olof 5061d 15h /
338 root 5853d 20h /
337 root 5909d 22h /
336 Added old uploaded documents to new repository. root 5911d 02h /
335 New directory structure. root 5911d 02h /
334 Minor fixes for Icarus simulator. igorm 7359d 04h /
333 Some small fixes + some troubles fixed. igorm 7359d 16h /

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