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Rev Log message Author Age Path
362 added Makefiles to build project unneback 5068d 08h /
361 created branch unneback unneback 5068d 08h /
360 Added partial implementation of the debug register from ORPSoC olof 5069d 07h /
359 Verilator linting fixes olof 5071d 09h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 5072d 23h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 5072d 23h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 5073d 01h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 5073d 02h /
354 Whitespace cleanup olof 5073d 02h /
353 Inherit fixes for bit width of constants from ORPSoC olof 5075d 04h /
352 Removed delayed assignments from rtl code olof 5079d 10h /
351 Turn defines into parameters in eth_cop olof 5088d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 5088d 00h /
349 Make all parameters configurable from top level olof 5089d 01h /
348 Added option to dump VCD files olof 5090d 00h /
347 Added information about running with Icarus Verilog olof 5090d 00h /
346 Updated project location olof 5090d 03h /
345 Temporarily disable failing tests olof 5090d 04h /
344 bit 9 in phy control register is self clearing olof 5096d 06h /
343 Address miss should not be asserted on short frames olof 5100d 02h /

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