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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3698d 00h /
363 quartus project files unneback 3698d 08h /
362 added Makefiles to build project unneback 3698d 09h /
361 created branch unneback unneback 3698d 09h /
360 Added partial implementation of the debug register from ORPSoC olof 3699d 07h /
359 Verilator linting fixes olof 3701d 10h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3703d 00h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3703d 00h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3703d 02h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3703d 02h /
354 Whitespace cleanup olof 3703d 03h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3705d 04h /
352 Removed delayed assignments from rtl code olof 3709d 10h /
351 Turn defines into parameters in eth_cop olof 3718d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3718d 01h /
349 Make all parameters configurable from top level olof 3719d 01h /
348 Added option to dump VCD files olof 3720d 00h /
347 Added information about running with Icarus Verilog olof 3720d 01h /
346 Updated project location olof 3720d 03h /
345 Temporarily disable failing tests olof 3720d 04h /

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